STM32F103T8U7TR 查看數據表（PDF） - STMicroelectronics
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STM32F103T8U7TR
STMicroelectronics
STM32F103T8U7TR Datasheet PDF : 123 Pages
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Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
Figure 26. Asynchronous multiplexed PSRAM/NOR read waveforms
tw(NE)
FSMC_NE
tv(NOE_NE)
t h(NE_NOE)
FSMC_NOE
FSMC_NWE
FSMC_A[25:16]
FSMC_NBL[1:0]
FSMC_AD[15:0]
FSMC_NADV
t w(NOE)
tv(A_NE)
tv(BL_NE)
Address
NBL
th(A_NOE)
th(BL_NOE)
t v(A_NE)
Address
t v(NADV_NE)
tw(NADV)
tsu(Data_NE)
tsu(Data_NOE)
Data
th(AD_NADV)
th(Data_NE)
th(Data_NOE)
ai14892b
Table 33. Asynchronous multiplexed PSRAM/NOR read timings(1)(2)
Symbol
Parameter
Min
Max
Unit
tw(NE)
tv(NOE_NE)
tw(NOE)
th(NE_NOE)
tv(A_NE)
tv(NADV_NE)
tw(NADV)
th(AD_NADV)
FSMC_NE low time
FSMC_NEx low to FSMC_NOE low
FSMC_NOE low time
FSMC_NOE high to FSMC_NE high hold time
FSMC_NEx low to FSMC_A valid
FSMC_NEx low to FSMC_NADV low
FSMC_NADV low time
FSMC_AD (address) valid hold time after
FSMC_NADV high
th(A_NOE)
Address hold time after FSMC_NOE high
th(BL_NOE) FSMC_BL hold time after FSMC_NOE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
tsu(Data_NE) Data to FSMC_NEx high setup time
tsu(Data_NOE) Data to FSMC_NOE high setup time
th(Data_NE) Data hold time after FSMC_NEx high
th(Data_NOE) Data hold time after FSMC_NOE high
1. CL = 15 pF.
2. Based on characterization, not tested in production.
7THCLK – 2 7THCLK + 2 ns
3THCLK – 0.5 3THCLK + 1.5 ns
4THCLK – 1 4THCLK + 2 ns
–1
ns
0
ns
3
5
ns
THCLK –1.5 THCLK + 1.5 ns
THCLK
ns
THCLK
ns
0
ns
0
ns
2THCLK + 24
ns
2THCLK + 25
ns
0
ns
0
ns
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Doc ID 14611 Rev 7
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