STM32F103V8H6TR 查看數據表（PDF） - STMicroelectronics

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STM32F103V8H6TR

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

Electrical characteristics

STM32F103xC, STM32F103xD, STM32F103xE

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up

performance:

● A supply overvoltage is applied to each power supply pin

● A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Table 44. Electrical sensitivities

Symbol

Parameter

Conditions

LU

Static latch-up class TA +105 °C conforming to JESD78A

Class

II level A

5.3.13 I/O port characteristics

General input/output characteristics

Unless otherwise specified, the parameters given in Table 45 are derived from tests

performed under the conditions summarized in Table 10. All I/Os are CMOS and TTL

compliant.

Table 45. I/O static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

VIL Input low level voltage

–0.5

Standard IO input high level voltage

TTL ports

2

VIH IO FT(1) input high level voltage

2

0.8

VDD+0.5

5.5V

VIL Input low level voltage

VIH Input high level voltage

Standard IO Schmitt trigger voltage

hysteresis(2)

Vhys

IO FT Schmitt trigger voltage

hysteresis(2)

CMOS ports

–0.5

0.65 VDD

200

5% VDD(3)

0.35 VDD

VDD+0.5

Ilkg Input leakage current (4)

VSS  VIN  VDD

Standard I/Os

VIN= 5 V, I/O FT

RPU Weak pull-up equivalent resistor(5)

VIN VSS

30

RPD Weak pull-down equivalent resistor(5)

VIN VDD

30

1

3

40

50

40

50

CIO I/O pin capacitance

5

1. FT = Five-volt tolerant.

2. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.

3. With a minimum of 100 mV.

4. Leakage could be higher than max. if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

Unit

V

V

mV

mV

µA

k

k

pF

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Doc ID 14611 Rev 7

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