STM32F103VC 查看數據表（PDF） - STMicroelectronics

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STM32F103VC

Medium-density performance line ARM-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

STMicroelectronics 

STM32F103xC, STM32F103xD, STM32F103xE

Electrical characteristics

Table 53. I2S characteristics

Symbol

Parameter

Conditions

DuCy(SCK)

I2S slave input clock duty

cycle

fCK

1/tc(CK)

I2S clock frequency

Slave mode

Master mode (data: 16 bits,

Audio frequency = 48 kHz)

Slave mode

tr(CK)

tf(CK)

tv(WS) (1)

I2S clock rise and fall time

WS valid time

th(WS) (1)

WS hold time

tsu(WS) (1)

th(WS) (1)

tw(CKH) (1)

tw(CKL) (1)

WS setup time

WS hold time

CK high and low time

tsu(SD_MR) (1) Data input setup time

tsu(SD_SR) (1)

th(SD_MR)(1)(2)

th(SD_SR) (1)(2)

Data input setup time

Data input hold time

tv(SD_ST) (1)(2) Data output valid time

Capacitive load CL = 50 pF

Master mode

Master mode

Slave mode

Slave mode

I2S2

I2S3

Master fPCLK= 16 MHz, audio

frequency = 48 kHz

Master receiver

I2S2

I2S3

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable

edge)

th(SD_ST) (1)

Data output hold time

Slave transmitter (after enable

edge)

tv(SD_MT) (1)(2) Data output valid time

Master transmitter (after enable

edge)

th(SD_MT) (1) Data output hold time

Master transmitter (after enable

edge)

1. Based on design simulation and/or characterization results, not tested in production.

2. Depends on fPCLK. For example, if fPCLK=8 MHz, then TPCLK = 1/fPLCLK =125 ns.

Min

30

1.522

0

3

2

0

4

0

312.5

345

2

6.5

1.5

0

0.5

11

0

Max

Unit

70

%

1.525

6.5

8

MHz

ns

18

3

Doc ID 14611 Rev 7

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