M1AGL250V2-CSG144ES 查看數據表（PDF） - Microsemi Corporation

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M1AGL250V2-CSG144ES

IGLOO Low Power Flash FPGAs with Flash* Freeze Technology

Microsemi Corporation 

IGLOO Low Power Flash FPGAs

Fully Registered I/O Buffers with Synchronous Enable and

Asynchronous Clear

Data

Enable

CLK

CLR

DOUT

CC

D

Q

DFN1E1C1

Y

EE

Core

Array

Data_out FF

D

Q

DFN1E1C1

GG

E

E

EOUT

BB

CLR

CLR

LL

HH

AA

DD

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

INBUF

JJ

D

Q

DFN1E1C1

KK

E

CLR

INBUF

CLKBUF

Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

Figure 2-17 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Revision 23

2- 85

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