GL811USB 查看數據表（PDF） - Genesys Logic

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GL811USB

USB 2.0 to ATA / ATAPI Bridge Controller

Genesys Logic 

GL811USB – USB 2.0 to ATA / ATAPI Bridge Controller

- Signal transition (asserted or negated)

- Data transition (asserted or negated)

- Data valid

- Undefined but not necessarily released

- Asserted, negated or released

- Released

- The “other” condition if a signal is shown with no change

All signals are shown with the asserted condition facing to the top of the page. The

negated condition is shown towards the bottom of the page relative to the asserted

condition.

The interface uses a mixture of negative and positive signals for control and data. The

terms asserted and negated are used for consistency and are independent of

electrical characteristics.

In all timing diagrams, the lower line indicates negated, and the upper line indicates

asserted. The following illustrates the representation of a signal named Test going

from negated to asserted and back to negated, based on the polarity of the signal.

Test

> VIH

< VIL

Test_

< VIL

> VIH

Assert

Assert

Negate

Negate

©2000-2002 Genesys Logic Inc.—All rights reserved.

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