FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

INDEX

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xEF

0xF0

TYPE

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

HARD

RESET

-

-

-

-

-

-

-

-

-

Vcc POR

-

-

-

-

-

-

-

-

-

Vtr POR

-

-

-

-

-

-

-

-

-

Vbat

POR

0x01

0x01

0x01

0x01

0x00

0x01

0x01

0x00

0x00

SOFT

RESET

-

-

-

-

-

-

-

-

-

CONFIGURATION

REGISTER

GP11 3

GP12 3

GP13 3

GP14 3

GP15 3

GP16 3

GP17 3

GP_INT2 3

GP_INT1 3

0xF1

R/W

0x00

0x00

0x00

-

-

WDT_UNITS

0xF2

R/W

0x00

0x00

0x00

-

-

WDT_VAL

0xF3

0xF4

0xF6

0xF9

0xFA

R/W

R/W(1)

R/W

R/W

R/W

0x00

0x00

-

-

-

0x00

0x00

-

-

-

0x00

0x00

-

-

-

-

-

0x00

0x00

0x00

-

WDT_CFG

-

WDT_CTRL

-

GP1 3

-

GP5 3

-

GP6 3

0x30

R/W

LOGICAL DEVICE A CONFIGURATION REGISTERS (ACPI)

0x00

0x00

0x00

-

0x00 Activate 4

0x60,

0x61 (2)

R/W

0x70

R/W

0x00,

0x00

-

0x00,

0x00

-

0x00,

0x00

-

-

0x00

0x00,

0x00

-

Primary Base I/O

Address

PM1_BLK

Primary Interrupt Select 3

0xF0

R/W

-

-

-

0x00

-

Sleep/Wake

Configuration 3

Notes

0) CR22 Bit 5 is reset on Vtr POR only

1) This register contains some bits which are read or write only.

2) Register 60 is the high byte; 61 is the low byte. For example to set the primary base address to

1234h, write 12h into 60, and 34h into 61.

3) These configuration registers are powered by Vtr and battery backed up.

4) The Activate bit for Logical Device A does not effect the generation of an interrupt (SCI).

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