FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

1. The GAP2 written to a perpendicular drive

during a write operation will depend upon the

programmed data rate.

2. The write pre-compensation given to a

perpendicular mode drive will be 0ns.

3. For D0-D3 programmed to "0" for

conventional mode drives any data written

will be at the currently programmed write

pre-compensation.

Note: Bits D0-D3 can only be overwritten when

OW is programmed as a "1".If either

GAP or WGATE is a "1" then D0-D3 are

ignored.

Software and hardware resets have the

following effect on the PERPENDICULAR

MODE COMMAND:

1. "Software" resets (via the DOR or DSR

registers) will only clear GAP and WGATE

bits to "0". D0-D3 are unaffected and retain

their previous value.

2. "Hardware" resets will clear all bits

(GAP, WGATE and D0-D3) to "0", i.e all

conventional mode.

WGATE

0

0

1

1

TABLE 32 - EFFECTS OF WGATE AND GAP BITS

GAP

MODE

PORTION OF GAP 2

LENGTH OF GAP2 WRITTEN BY WRITE DATA

FORMAT FIELD

OPERATION

0 Conventional

1 Perpendicular

(500 Kbps)

0 Reserved

(Conventional)

1 Perpendicular

(1 Mbps)

22 Bytes

22 Bytes

22 Bytes

41 Bytes

0 Bytes

19 Bytes

0 Bytes

38 Bytes

69

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