FDC37B78X 查看數據表（PDF） - SMSC -> Microchip

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FDC37B78X

Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR

SMSC -> Microchip 

FIFO POLLED MODE OPERATION

With FCR bit 0 = "1" resetting IER bits 0, 1, 2 or

3 or all to zero puts the UART in the FIFO

Polled Mode of operation. Since the RCVR and

XMITTER are controlled separately, either one

or both can be in the polled mode of operation.

In this mode, the user's program will check

RCVR and XMITTER status via the LSR. LSR

definitions for the FIFO Polled Mode are as

follows:

- Bit 0=1 as long as there is one byte in the

RCVR FIFO.

- Bits 1 to 4 specify which error(s) have

occurred. Character error status is handled

the same way as when in the interrupt

mode, the IIR is not affected since EIR bit

2=0.

- Bit 5 indicates when the XMIT FIFO is

empty.

- Bit 6 indicates that both the XMIT FIFO and

shift register are empty.

- Bit 7 indicates whether there are any errors

in the RCVR FIFO.

There is no trigger level reached or timeout

condition indicated in the FIFO Polled Mode,

however, the RCVR and XMIT FIFOs are still

fully capable of holding characters.

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