COM20022V-HT 查看數據表（PDF） - SMSC -> Microchip
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COM20022V-HT Datasheet PDF : 88 Pages
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AD0-AD2,
D3-D15
nCS
ALE
nDS
DIR
nIOCS16
TIMING DIAGRAMS
VALID
t1
t2,
t4
VALID DATA
t3
t12
t11
t6
t5
t13
Previous Value
t9
t15 t16
Invalid
t8
Valid Value
t7
t14
Note 2
t10
MUST BE: BUSTMG pin = HIGH and RBUSTMG bit = 0
Parameter
min
max units
t1 Address Setup to ALE Low
t2 Address Hold from ALE Low
t3 nCS Setup to ALE Low
t4 nCS Hold from ALE Low
t5 ALE Low to nDS Low
t6 nDS Low to Valid Data
t7 nDS High to Data High Impedance
t8 Cycle Time (nDS Low to Next Time Low)
t9 DIR Setup to nDS Active
t10 DIR Hold from nDS Inactive
t11 ALE High Width
t12 ALE Low Width
t13 nDS Low Width
t14 nDS High Width
t15 nIOCS16 Hold Delay from ALE Low
t16 nIOCS16 Output Delay from ALE Low
20
nS
10
nS
10
nS
10
nS
15
nS
40
nS
0
20
nS
4TARB*
nS
10
nS
10
nS
20
nS
20
nS
60
nS
20
nS
0
nS
40
nS
* TARB is the Arbitration Clock Period
TARB is identical to Topr if SLOW ARB = 0
TARB is twice Topr if SLOW ARB = 1
Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits
Note 1: The Microcontroller typically accesses the COM20022 on every other cycle.
Therefore, the cycle time specified in the microcontroller's datasheet
should be doubled when considering back-to-back COM20022 cycles.
Note 2:
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FIGURE 16 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE
62
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