XTAL1
4.0V
t1
t2
1.0V
t3
50% of VDD
Parameter
t1
Input Clock High Time
t2
Input Clock Low Time
t3
Input Clock Period*
t4
Input Clock Frequency*
t5
Frequency Accuracy*
min typ
20
20
50
10
-200
max
100
20
200
units
nS
nS
nS
MHz
((
Note*: Input clock frequency must be 20 MHz (01 100ppm or better) to use the internal Clock Multiplier.
/ ! (( &
FIGURE 26 - TTL INPUT TIMING ON XTAL1 PIN
t1
nRESET
nINTR
t2
Parameter
min typ
t1
nRESET Pulse Width***
t2
nINTR High to Next nINTR Low EF = 0
EF = 1
5TXTL*
TDR**/2
4TXTL*
Note*: TXTL is period of external XTAL oscillation frequency.
Note**: TDR is period of Data Rate (i.e. at 2.5 Mbps, TDR = 400 nS)
Note***: When the power is turned on, t1 is measured from stable XTAL
- ./&!-&
FIGURE 27 - RESET AND INTERRUPT TIMING
max units
76