COM20022V-HT 查看數據表（PDF） - SMSC -> Microchip
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COM20022V-HT Datasheet PDF : 88 Pages
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EF: Enable/Disable the new internal operation timing and logic refinements. EF=0: (Default) Disable
the new internal operation timing (the timing is the same as in the COM20020 Rev. B); EF=1: Enable
the new internal operation timing.
The EF bit controls the following timing/logic refinements in the COM20022:
A) Extend Interrupt Disable Time
While the interrupt is active (nINTR pin=0), the interrupt is disabled by writing the Clear Tx/Rx interrupt
and Clear Flag command and by reading the Next-ID register. This minimum disable time is changed
by the Data Rate. For example, it is 200nS at 2.5Mbps and 50nS at 10Mbps. The 50nS width will be too
short to for the Interrupt to be seen.
Setting the EF bit will change the minimum disable time to always be more than 200nS even if the Data
Rate is 10Mbps . This is done by changing the clock which is supplied to the Interrupt Disable logic.
The frequency of this clock is always 20MHz even if the data rate is 10Mbps.
B) Synchronize the Pre-Scalar Output
The Pre-Scalar is used to change the data rate. The output clock is selected by CKP3-1 bits in the
Setup1 register. The CKP3-1 bits are changed by writing the Setup1 register from outside the CPU. It's
not synchronized between the CPU and COM20022. Thus, changing the CKP2-0 timing does not
synchronize with the internal clocks of Pre-Scalar, and changing CKP2-0 may cause spike noise to
appear on the output clock line.
Setting the EF bit will include flip-flops inserted between the Setup1 register and Pre-Scalar for
synchronizing the CKP2-0 with Pre-Scalar’s internal clocks.
Never change the CKP2-0 when the data rate is over 5 Mbps. They must all be zero.
C) Shorten The Write Interval Time To The Command Register
The COM20022 limits the write interval time for continuous writing to the Command register. The
minimum interval time is changed by the Data Rate. It's 100 nS at the 2.5 Mbps and 1.6 #S at the
156.25 Kbps. This 1.6 #S is very long for CPU.
Setting the EF bit will change the clock source from OSCK clock (8 times frequency of data rate) to
XTAL clock which is not changed by the data rate, such that the minimum interval time becomes 100
nS.
D) Eliminate The Write Prohibition Period For The Enable Tx/Rx Commands
The COM20022 has a write prohibition period for writing the Enable Transmit/Receive Commands. This
period is started by the TA or RI bit (Status Reg.) returning to High. This prohibition period is caused by
setting the TA/RI bit with an internal pulse signal. It is 3.2 #S at 156.25 Kbps. This period may be a
problem when using interrupt processing. The interrupt occurs when the RI bit returns to High. The
CPU writes the next Enable Receive Command to the other page immediately. In this case, the interval
time between the interrupt and writing Command is shorter than 3.2 #S.
Setting the EF bit will cause the TA/RI bit to return to High upon release of the internal pulse signal for
setting the TA/RI bit, instead of at the start of the pulse. This is illustrated in figure 30
on the following page.
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