M50FLW080AN5 查看數據表（PDF） - STMicroelectronics
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M50FLW080AN5
STMicroelectronics
M50FLW080AN5 Datasheet PDF : 64 Pages
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M50FLW080A, M50FLW080B
Status Register
5.6
Program Suspend status (bit SR2)
This bit indicates that a Program operation has been suspended, and that it is waiting to be
resumed. The Program Suspend Status should only be considered valid when the
Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). After a
Program/Erase Suspend command is issued, the memory may still complete the operation
instead of entering the Suspend mode.
When the Program Suspend Status bit is ‘0’, the Program/Erase Controller is active, or has
completed its operation. When the bit is ‘1’, a Program/Erase Suspend command has been
issued and the memory is waiting for a Program/Erase Resume command.
When a Program/Erase Resume command is issued, the Program Suspend Status bit
returns to ‘0’.
5.7
Block/Sector Protection status (bit SR1)
The Block/Sector Protection Status bit can be used to identify if the Program or Erase
operation has tried to modify the contents of a protected block or sector. When the
Block/Sector Protection Status bit is reset to ‘0’, no Program or Erase operations have been
attempted on protected blocks or sectors since the last Clear Status Register command or
hardware reset. When the Block/Sector Protection Status bit is ‘1’, a Program or Erase
operation has been attempted on a protected block or sector.
Once it is set to ‘1’, the Block/Sector Protection Status bit can only be reset to ‘0’ by a Clear
Status Register command or by a hardware reset. If it is set to ‘1’, it should be reset before a
new Program or Erase command is issued, otherwise the new command will appear to have
failed, too.
Using the A/A Mux Interface, the Block/Sector Protection Status bit is always ‘0’.
5.8
Reserved (bit SR0)
Bit 0 of the Status Register is reserved. Its value should be masked.
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