MAX152CPP 查看數據表（PDF） - Maxim Integrated

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MAX152CPP

+3V, 8-Bit ADC with 1µA Power-Down

Maxim Integrated 

+3V, 8-Bit ADC with 1µA Power-Down

tWR

WR

INT

D0-D7

OLD DATA

tIHWR

tINTL

tP

tID

NEW DATA

+3V

0.1µF

VIN+

VIN-

4.7µF

1 VIN

10 GND

20 VDD MAX152

12 VREF+

11 VREF-

Figure 6. Stand-Alone Mode Timing (CS = RD = 0) (MODE = 1)

A minimum acquisition time (tP) is required from INT

going low to the start of another conversion (WR going

low).

Options for reading data from the converter include the

following:

Using Internal Delay

The µP waits for the INT output to go low before read-

ing the data (Figure 4). INT goes low after the rising

edge of WR, indicating that the conversion is complete

and the result is available in the output latch. With CS

low, data outputs D0-D7 can be accessed by pulling

RD low. INT is then reset by the rising edge of CS or

RD.

Fastest Conversion: Reading Before Delay

An external method of controlling the conversion time is

shown in Figure 5. The internally generated delay

tINTL varies slightly with temperature and supply volt-

age, and can be overridden with RD to achieve the

fastest conversion time. RD is brought low after the ris-

ing edge of WR, but before INT goes low. This com-

pletes the conversion and enables the output buffers

(D0-D7) that contain the conversion result. INT also

goes low after the falling edge of RD and is reset on the

rising edge of RD or CS. The total conversion time is

therefore: tCWR = tWR (600ns) + tRD (800ns) + tACC1

(400ns) = 1800ns.

Stand-Alone Operation

Besides the two standard WR-RD mode options, stand-

alone operation can be achieved by connecting CS

and RD low (Figure 6). A conversion is initiated by

pulling WR low. Output data can be read by either

edge of the next WR pulse.

Figure 7a. Power Supply as Reference

+3V

4.7

µF

VIN+

VIN-

10 1

GND VIN

20 VDD

0.1

7

µF

8

6 +2.5V 12 VREF+

1 LM10 2

3

0.1

MAX152

µF

4

VREF-

11

Figure 7b. External Reference, +2.5V Full Scale

VIN+

+3V

0.1µF

4.7µF

VIN- 1.2V

1 VIN

10 GND

20 VDD MAX152

12

VREF+

11 VREF-

*CURRENT PATH MUST STILL

EXIST FROM VIN- TO GND.

0.1µF

0.1µF

Figure 7c. Input Not Referenced to GND

+3V

PWRDN

MAX872

+

C1

2.2µF

VDD

MAX152

VREF+

VREF-

PWRDN

N

MTD3055EL

Figure 7d. An N-channel MOSFET switches off the reference

load during power-down.

8 _______________________________________________________________________________________

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