PIC16F874T-10/ISP 查看數據表（PDF） - Microchip Technology

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PIC16F874T-10/ISP

28/40-Pin 8-Bit CMOS FLASH Microcontrollers

Microchip Technology 

PIC16F87X

2.2.2.7 PIR2 Register

The PIR2 register contains the flag bits for the CCP2

interrupt, the SSP bus collision interrupt and the

EEPROM write operation interrupt.

.

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the global

enable bit, GIE (INTCON<7>). User soft-

ware should ensure the appropriate inter-

rupt flag bits are clear prior to enabling an

interrupt.

REGISTER 2-7:

PIR2 REGISTER (ADDRESS 0Dh)

U-0

R/W-0

U-0

— Reserved —

bit 7

R/W-0

EEIF

R/W-0

BCLIF

U-0

U-0

R/W-0

—

—

CCP2IF

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2-1

bit 0

Unimplemented: Read as '0'

Reserved: Always maintain this bit clear

Unimplemented: Read as '0'

EEIF: EEPROM Write Operation Interrupt Flag bit

1 = The write operation completed (must be cleared in software)

0 = The write operation is not complete or has not been started

BCLIF: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred in the SSP, when configured for I2C Master mode

0 = No bus collision has occurred

Unimplemented: Read as '0'

CCP2IF: CCP2 Interrupt Flag bit

Capture mode:

1 = A TMR1 register capture occurred (must be cleared in software)

0 = No TMR1 register capture occurred

Compare mode:

1 = A TMR1 register compare match occurred (must be cleared in software)

0 = No TMR1 register compare match occurred

PWM mode:

Unused

Legend:

R = Readable bit

- n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS30292C-page 24

 2001 Microchip Technology Inc.

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