PSD834F515MI 查看數據表（PDF） - STMicroelectronics

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PSD834F515MI

Flash In-System Programmable (ISP) Peripherals for 8-bit MCUs, 5V

STMicroelectronics 

PSD813F2, PSD833F2, PSD834F2, PSD853F2, PSD854F2

Complex PLD (CPLD)

The CPLD can be used to implement system logic

functions, such as loadable counters and shift reg-

isters, system mailboxes, handshaking protocols,

state machines, and random logic. The CPLD can

also be used to generate three External Chip Se-

lect (ECS0-ECS2), routed to Port D.

Although External Chip Select (ECS0-ECS2) can

be produced by any Output Macrocell (OMC),

these three External Chip Select (ECS0-ECS2) on

Port D do not consume any Output Macrocells

(OMC).

As shown in Figure 13., page 34, the CPLD has

the following blocks:

■ 24 Input Macrocells (IMC)

■ 16 Output Macrocells (OMC)

■ Macrocell Allocator

■ Product Term Allocator

■ AND Array capable of generating up to 137

product terms

■ Four I/O Ports.

Each of the blocks are described in the sections

that follow.

The Input Macrocells (IMC) and Output Macrocells

(OMC) are connected to the PSD internal data bus

and can be directly accessed by the MCU. This

enables the MCU software to load data into the

Output Macrocells (OMC) or read data from both

the Input and Output Macrocells (IMC and OMC).

This feature allows efficient implementation of sys-

tem logic and eliminates the need to connect the

data bus to the AND Array as required in most

standard PLD macrocell architectures.

Figure 15. Macrocell and I/O Port

PRODUCT TERMS

FROM OTHER

MACROCELLS

MCU ADDRESS / DATA BUS

CPLD MACROCELLS

PRODUCT TERM

ALLOCATOR

PT PRESET

MCU DATA IN

MCU LOAD

DATA

LOAD

CONTROL

UP TO 10

PRODUCT TERMS

POLARITY

SELECT

PT

CLOCK

GLOBAL

CLOCK

CLOCK

SELECT

PT CLEAR

MACROCELL

OUT TO

MCU

PR DI LD

D/T

Q

D/T/JK FF

SELECT

CK

CL

COMB.

/REG

SELECT

CPLD

OUTPUT

MACROCELL

TO

I/O PORT

ALLOC.

PT OUTPUT ENABLE (OE)

MACROCELL FEEDBACK

I/O PORT INPUT

PT INPUT LATCH GATE/CLOCK

TO OTHER I/O PORTS

I/O PORTS

LATCHED

ADDRESS OUT

DATA

WR

DQ

MUX

CPLD OUTPUT

I/O PIN

PDR

INPUT

SELECT

DQ

DIR

WR

REG.

INPUT MACROCELLS

QD

ALE/AS

QD

G

AI02874

36/110

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