PSD913G3V-B-90UI 查看數據表（PDF） - STMicroelectronics
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PSD913G3V-B-90UI Datasheet PDF : 94 Pages
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PSD9XX Family
Figure 9. PLD Block Diagrams
DATA
BUS
8
PAGE
REGISTER
8
DECODE PLD
57
4
1
1
Preliminary Information
FLASH MEMORY SELECTS
SECONDARY FLASH MEMORY SELECTS
SRAM SELECT
CSIOP SELECT
GENERAL
PURPOSE PLD
GPLD
PLD OUT 8
57
PLD OUT 8
PLD OUT 3
PORT C PLD INPUT 8
PORT A PLD INPUT 8
PORT B PLD INPUT 8
PORT D PLD INPUT 3
Figure 10. DPLD Logic Array
I /O PORTS (PORT A,B,C)
(INPUTS)
(24)
PGR0 - PGR7
(8)
A[15:0] *
(16)
PD[2:0] (ALE,CLKIN,CSI)
(3)
PDN (APD OUTPUT)
(1)
CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (3)
RESET
(1)
RD_BSY
(1)
*NOTE: The address inputs are A[19:4] in 80C51XA mode.
32
PORT A
PORT B
PORT D
PORT C
3
CSBOOT 0
3
CSBOOT 1
4 SECONDARY
FLASH MEMORY
3
CSBOOT 2
SECTOR SELECTS
3
CSBOOT 3
3
FS0
3
3
3
8 FLASH MEMORY
3
SECTOR SELECTS
3
3
3
FS7
2
RS0
SRAM SELECT
CSIOP
I/O DECODER
SELECT
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