PSD913G3V-C-90JI 查看數據表（PDF） - STMicroelectronics

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PSD913G3V-C-90JI

Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs

STMicroelectronics 

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

Figure 23. APD Logic Block

Preliminary Information

APD EN

PMMR0 BIT 1=1

TRANSITION

DETECTION

ALE

RESET

CSI

CLKIN

EDGE

DETECT

DISABLE

MAIN FLASH/

SECONDARY FLASH /SRAM

CLR PD

APD

COUNTER

PD

DISABLE BUS

INTERFACE

SECONDARY

FLASH SELECT

PLD

MAIN FLASH

SELECT

SRAM SELECT

POWER DOWN

(PDN) SELECT

Figure 24. Enable Power Down Flow Chart

RESET

Enable APD

Set PMMR0 Bit 1 = 1

OPTIONAL

Disable desired inputs to PLD

by setting PMMR0 bit 4

and PMMR2 bits 2 through 6.

No

ALE/AS idle

for 15 CLKIN

clocks?

Yes

PSD in Power

Down Mode

56

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