Z86M1720ASC 查看數據表（PDF） - Zilog

零件编号

产品描述 (功能)

生产厂家

Z86M1720ASC

PCMCIA Interface Solution

Zilog 

Z86017/Z16017 PCMCIA Interface Solution

Product Specification

59

EEPROM Register

Address: SELECT 18h

Name: Window 3 Control Register

Type: Write/Read

Table 38. Window 3 Control Register: Address 18h

Bit Placement Bit Name

Description

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bits 7-6

DIS_PAC3

When set to 1, this bit disables Port 3 address control and

decoder.

EN_PAC3_MEM

When this bit is set to 1, Memory mode decoder is enabled.

When it is cleared, I/O mode decoder is enabled.

EN_PAC3_16+

When this bit is set, data swapping is provided internal to

the chip during data reads from the low byte of the ATA

bus to the PCMCIA bus high byte, and from the high byte

of the PCMCIA bus to the low byte of the ATA bus during

data writes. When this bit is cleared, it is high byte to high

byte and low byte to low byte.

READ_PROTECT

This bit allows two cards to be read from the same address.

When this bit is set, it prevents the PCMCIA bus from

becoming active.

EN_PAC3_ADDR_COMP When this bit is set, use address compare logic; when it is

cleared, acknowledge all PCMCIA chip selects.

EN_PAC3_HCS

When this bit is set, HCS1 is used as an external chip

select; when it is cleared, HCS0 is used as an external chip

select.

Number of wait states (in Master Clock periods) inserted

on the PCMCIA bus.

Programming Internal Registers

PS012002-1201

Share Link: