Z80230 查看數據表（PDF） - Zilog

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Z80230

Zilog SCC Serial Communication Controller

Zilog 

Application Note

The Z180™ Interfaced with the SCC at MHZ

Interrupt Condition

7

IP

Set

IEI High?

IUS

Set

CPU Read, Write, or Reset

INT

Active

Wait For CPU

/INTACK Cycle

/INTACK * IEI * /RD

IP

Cleared

IEO High?

IUS

Cleared

Return To Main Program

Figure 12. SCC Interrupt Status Diagram

The SCC uses /INTACK (Interrupt Acknowledge) for

recognition of an interrupt acknowledge cycle. This pin,

used with /RD, allows the SCC to gate its interrupt vector

onto the data bus. An active /RD signal during an interrupt

acknowledge cycle performs two functions. First, it allows

the highest priority device requesting an interrupt to place

its vector on the data bus. Secondly, it sets the IUS bit in

the highest priority device to show the device is now under

service.

UM010901-0601

6-37

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