LCMXO2280C-5M100CES 查看數據表（PDF） - Lattice Semiconductor

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LCMXO2280C-5M100CES

MachXO Family Data Sheet

Lattice Semiconductor 

Lattice Semiconductor

DC and Switching Characteristics

MachXO Family Data Sheet

Switching Test Conditions

Figure 3-6 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Figure 3-5.

Figure 3-6. Output Test Load, LVTTL and LVCMOS Standards

VT

R1

DUT

Test Poi nt

CL

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

R1

CL

Timing Ref.

VT

LVTTL, LVCMOS 3.3 = 1.5V

—

LVCMOS 2.5 = VCCIO/2

—

LVTTL and LVCMOS settings (L -> H, H -> L)

∞

0pF LVCMOS 1.8 = VCCIO/2

—

LVCMOS 1.5 = VCCIO/2

—

LVCMOS 1.2 = VCCIO/2

—

LVTTL and LVCMOS 3.3 (Z -> H)

LVTTL and LVCMOS 3.3 (Z -> L)

1.5

VOL

VOH

Other LVCMOS (Z -> H)

Other LVCMOS (Z -> L)

188

0pF VCCIO/2

VCCIO/2

VOL

VOH

LVTTL + LVCMOS (H -> Z)

VOH - 0.15

VOL

LVTTL + LVCMOS (L -> Z)

VOL - 0.15

VOH

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-18

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