M48TPC1TR 查看數據表（PDF） - STMicroelectronics

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M48TPC1TR

5V PC REAL TIME CLOCK

STMicroelectronics 

REGISTER A

MSB

BIT7

UIP

BIT6

OSC2

BIT5

OSC1

BIT4

OSC0

BIT3

RS3

BIT2

RS2

M48T86

BIT1

RS1

BIT0

RS0

UIP. Update in Progress

The Update in Progress (UIP) bit is a status flag

that can be monitored. When the UIP bit is one,

the update transfer will soon occur. When UIP isa

zero, the update transfer will not occur for at least

244µs. The time, calendar, and alarm information

in RAM is fully available for access when the UIP

bit is zero. The UIP bit is read only and is not af-

fected by RST. Writing the SET bit in Register B to

a "1" inhibits any update transfer and clears the

UIP status bit.

OSC0, OSC1, OSC2. Oscillator Control

These three bits are used to control the oscillator

and reset the countdown chain. A pattern of "010"

enables operation by turning on the oscillator and

enabling the divider chain. A pattern of 11X turns

the oscillator on, but keeps the frequency divider

disabled. When "010" is written, the first update

begins after 500ms.

RS3, RS2, RS1, RS0

These four rate-selection bits select one of the 13

taps on the 15-stage divider or disable the divider

output. The tap selected may be used to generate

an output square wave (SQW pin) and/or a period-

ic interrupt. The user may do one of the following:

1. Enable the interrupt with the PIE bit;

or

2. Enable the SQW output with the SQWE bit;

or

3. Enable both at the same time and same rate;

or

4. Enable neither.

Table 10 lists the periodic interrupt rates and the

square wave frequencies that may be chosen with

the RS bits. These four read/write bits are not af-

fected by RST.

15/23

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