PIC16F1827T-E/ML 查看數據表（PDF） - Microchip Technology

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PIC16F1827T-E/ML

18/20/28-Pin Flash Microcontrollers with nanoWatt XLP Technology

Microchip Technology 

PIC16F/LF1826/27

FIGURE 25-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

RX/DT

pin

TX/CK pin

(SCKP = 0)

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

TX/CK pin

(SCKP = 1)

Write to

bit SREN

SREN bit

CREN bit ‘0’

‘0’

RCIF bit

(Interrupt)

Read

RCREG

Note:

Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.

TABLE 25-8: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER

RECEPTION

Name

APFCON0

APFCON1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

RXDTSEL SDO1SEL SS1SEL P2BSEL(1) CCP2SEL(1) P1DSEL

—

—

—

—

—

—

Bit 1

P1CSEL

—

Bit 0

CCP1SEL

TXCKSEL

Register

on Page

122

122

BAUDCON ABDOVF RCIDL

—

SCKP

BRG16

—

WUE

ABDEN

298

INTCON

GIE

PEIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

IOCIF

101

PIE1

PIR1

TMR1GIE

TMR1GIF

ADIE

ADIF

RCIE

RCIF

TXIE

TXIF

SSPIE

CCP1IE TMR2IE TMR1IE

102

SSPIF

CCP1IF TMR2IF TMR1IF

105

RCREG

EUSART Receive Data Register

292*

RCSTA

SPBRGL

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

297

BRG<7:0>

299*

SPBRGH

TRISB

TXSTA

Legend:

*

Note 1:

BRG<15:8>

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Master Reception.

Page provides register information.

PIC16F/LF1827 only.

299*

129

296

DS41391C-page 312

Preliminary

 2010 Microchip Technology Inc.

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