Z8F012APJ020SG 查看數據表（PDF） - Zilog
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Z8F012APJ020SG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
100
RXD
Parity Checker
Receive Shifter
Receiver Control
with Address Compare
Receive Data
Register
System Bus
Control Registers
Transmit Data
Register
Status Register
Baud Rate
Generator
TXD
CTS
DE
Transmit Shift
Register
Parity Generator
Transmitter Control
Figure 10. UART Block Diagram
Operation
The UART always transmits and receives data in an 8-bit data format, least-significant bit
first. An even or odd parity bit can be added to the data stream. Each character begins with
an active Low start bit and ends with either 1 or 2 active High stop bits. Figures 11 and 12
display the asynchronous data format employed by the UART without parity and with par-
ity, respectively.
PS022827-1212
PRELIMINARY
Operation
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