Z8F012APJ020SG 查看數據表（PDF） - Zilog
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Z8F012APJ020SG Datasheet PDF : 282 Pages
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Z8 Encore! XP® F082A Series
Product Specification
114
UART Status 0 Register
The UART Status 0 (UxSTAT0) and Status 1(UxSTAT1) registers, shown in Tables 65 and
66, identify the current UART operating configuration and status.
Table 65. UART Status 0 Register (U0STAT0)
Bit
7
6
5
4
3
2
1
0
Field
RDA
PE
OE
FE
BRKD TDRE
TXE
CTS
RESET
0
0
0
0
0
1
1
X
R/W
R
R
R
R
R
R
R
R
Address
F41H
Bit
[7]
RDA
[6]
PE
[5]
OE
[4]
FE
[3]
BRKD
Description
Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data Register
clears this bit.
0 = No parity error has occurred.
1 = A parity error has occurred.
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit and Stop bit(s)
are all 0s this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
PS022827-1212
PRELIMINARY
UART Control Register Definitions
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