Z8F041APJ020EG 查看數據表（PDF） - Zilog

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Z8F041APJ020EG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

182

RS-232 TX

RS-232 RX

RS-232

Transceiver

VDD

Open-Drain

Buffer

10 k

DBG Pin

Figure 25. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface; #2 of 2

DEBUG Mode

The operating characteristics of the devices in DEBUG Mode are:

• The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-

ecute specific instructions

• The system clock operates unless in STOP Mode

• All enabled on-chip peripherals operate unless in STOP Mode

• Automatically exits HALT Mode

• Constantly refreshes the Watchdog Timer, if enabled

Entering DEBUG Mode

The operating characteristics of the devices entering DEBUG Mode are:

• The device enters DEBUG Mode after the eZ8 CPU executes a BRK (Breakpoint) in-

struction

• If the DBG pin is held Low during the final clock cycle of system reset, the part enters

DEBUG Mode immediately (20-/28-pin products only)

Note: Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset (making

sure to account for any specified frequency error if using an internal oscillator) prevents a

false interpretation of an Autobaud sequence (see the OCD Auto-Baud Detector/Generator

section on page 183).

PS022827-1212

PRELIMINARY

Operation

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