Z8F012APJ020SG 查看數據表（PDF） - Zilog

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Z8F012APJ020SG

High-Performance 8-Bit Microcontrollers Z8 Encore! XP® F082A Series

Zilog 

Z8 Encore! XP® F082A Series

Product Specification

33

HALT Mode

Executing the eZ8 CPU’s HALT instruction places the device into HALT Mode, which

powers down the CPU but leaves all other peripherals active. In HALT Mode, the operat-

ing characteristics are:

• Primary oscillator is enabled and continues to operate

• System clock is enabled and continues to operate

• eZ8 CPU is stopped

• Program counter (PC) stops incrementing

• Watchdog Timer’s internal RC oscillator continues to operate

• If enabled, the Watchdog Timer continues to operate

• All other on-chip peripherals continue to operate, if enabled

The eZ8 CPU can be brought out of HALT Mode by any of the following operations:

• Interrupt

• Watchdog Timer time-out (interrupt or reset)

• Power-On Reset

• Voltage Brown-Out reset

• External RESET pin assertion

To minimize current in HALT Mode, all GPIO pins that are configured as inputs must be

driven to one of the supply rails (VCC or GND).

Peripheral-Level Power Control

In addition to the STOP and HALT modes, it is possible to disable each peripheral on each

of the Z8 Encore! XP F082A Series devices. Disabling a given peripheral minimizes its

power consumption.

Power Control Register Definitions

The following sections define the Power Control registers.

Power Control Register 0

Each bit of the following registers disables a peripheral block, either by gating its system

clock input or by removing power from the block. The default state of the low-power

PS022827-1212

PRELIMINARY

HALT Mode

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