OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor
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OR2T15B7BA352-DB Datasheet PDF : 200 Pages
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Data Sheet
November 2006
ORCA Series 2 FPGAs
Timing Characteristics (continued)
Table 39A. OR2CxxA and OR2TxxA Synchronous Memory Write Characteristics (SSPM and SDPM Modes)
OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C ≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.
OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤
+85 °C.
Speed
Parameter
Symbol
-3
-4
-5
-6
S Write Operation for Fast-RAM Mode1:
Maximum Frequency
E Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])2
Min Max Min Max Min Max Min Max
FFSCK
TFSCL
TFSCH
FMEMS_DEL
52.6 — 83.3 — 90.9 — 92.6 —
9.5 — 6.0 — 5.5 — 5.4 —
9.5 — 6.0 — 5.5 — 5.4 —
— 7.4 — 6.2 — 5.0 — 5.3
IC Write Operation for Normal RAM Mode:
Maximum Frequency
D Clock Low Time
Clock High Time
Clock to Data Valid (CK to F[3:0])
FSCK
TSCL
TSCH
MEMS_DEL
33.3 — 52.6 — 58.0 — 58.8 —
15.0 — 9.5 — 8.5 — 8.5 —
15.0 — 9.5 — 8.5 — 8.5 —
— 8.6 — 7.5 — 6.0 — 6.4
V Write Operation Setup Time:
E Address to Clock (A[3:0]/B[3:0] to CK) MEMS_ASET 0.0 — 0.0 — 0.0 — 0.0 —
Data to Clock (WD[3:0] to CK)
MEMS_DSET 0.0 — 0.0 — 0.0 — 0.0 —
Write Enable (WREN) to Clock
MEMS_WRSET 0.0 — 0.0 — 0.0 — 0.0 —
E (A4 to CK)
U Write-port Enable (WPE) to Clock
MEMS_PWRSET 0.0 — 0.0 — 0.0 — 0.0 —
(C0 to CK)
D Write Operation Hold Time:
IN Address to Clock (A[3:0]/B[3:0] to CK) MEMS_AHLD 3.0 — 2.2 — 2.0 — 1.9 —
Data to Clock (WD[3:0] to CK)
MEMS_DHLD 3.0 — 2.2 — 2.0 — 1.9 —
Write Enable (WREN) to Clock
MEMS_WRHLD 3.0 — 2.2 — 2.0 — 1.9 —
(A4 to CK)
T Write-port Enable (WPE) to Clock
MEMS_PWRHL 2.3 — 1.5 — 1.4 — 1.9 —
T (C0 to CK)
D
-7
Min Max
96.2 —
5.2 —
5.2 —
— 5.2
59.8 —
8.4 —
8.4 —
— 5.9
0.0 —
0.0 —
0.0 —
0.0 —
1.8 —
1.8 —
1.8 —
1.2 —
Unit
MHz
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. Readback of the configuration bit stream when simultaneously writing to a PFU in either SSPM fast mode or SDPM fast mode is not allowed.
C 2. Because the setup time of data into the latches/FFs is less than 0 ns, data written into the RAM can be loaded into a latch/FF in the same
N PFU on the next opposite clock edge (one-half clock period).
Table 39.B OR2TxxB Synchronous Memory Write Characteristics (SSPM and SDPM Modes)
E O OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C ≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.
LParameter
E C Write Operation for Fast-RAM Mode1:
Maximum Frequency
S IS Clock LowTime
Clock High Time
Clock to Data Valid (CK to F[3:0])2
D Write Operation for Normal RAM Mode:
Symbol
FFSCK
TFSCL
TFSCH
FMEMS_DEL
Speed
-7
-8
Min
Max
Min
Max
97.7
—
112.4
—
5.1
—
4.5
—
5.1
—
4.5
—
—
5.1
—
4.5
Unit
MHz
ns
ns
ns
Maximum Frequency
FSCK
60.8
—
69.9
—
MHz
Clock Low Time
TSCL
8.2
—
7.2
—
ns
Clock High Time
TSCH
8.2
—
7.2
—
ns
Clock to Data Valid (CK to F[3:0])
MEMS_DEL
—
5.1
—
4.5
ns
Lattice Semiconductor
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