ORCA Series 2 FPGAs
Data Sheet
November 2006
Interquad Routing (continued)
The PXH lines from the one quadrant can be con-
nected through a CIP to its counterpart in the opposite
PIC Interquad (MID) Routing
quadrant, providing a path that spans the array of PICs.
Since a passive CIP is used to connect the two PXH
Between the PICs in each quadrant, there is also con- lines, a 3-state signal can be routed on the two PXH
nectivity between the PIC routing and the interquad
routing. These blocks are called LMID (left), TMID
(top), RMID (right), and BMID (bottom). The TMID rout-
ing is shown in Figure 33. As with the hIQ and vIQ
S blocks, the only connectivity to the PIC routing is to the
global PXH and PXL lines.
lines in the opposite quadrants, and then connected
through this CIP. As with the hIQ and vIQ blocks, CIPs
and buffers allow nibble-wide connections between the
interquad lines, the XH lines, and the XL lines.
E PXL[1]
PXL[0]
IC PXH[3]
PXH[2]
D PXH[1]
PXH[0]
V PX4[3]
E PX4[2]
PX4[1]
PX4[0]
E U PX1[3]
PX1[2]
PX1[1]
PX1[0]
PXL[1]
PXL[0]
PXH[3]
PXH[2]
PXH[1]
PXH[0]
PX4[3]
PX4[2]
PX4[1]
PX4[0]
PX1[3]
PX1[2]
PX1[1]
PX1[0]
T D TIN HX4[3]
HX4[2]
C HX4[1]
N HX4[0]
HX4[3]
HX4[2]
HX4[1]
HX4[0]
SELDEISCO Figure 33.Top (TMID) Routing
5-4201(F).r4
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Lattice Semiconductor