OR2T15B7BA352-DB 查看數據表（PDF） - Lattice Semiconductor

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OR2T15B7BA352-DB

ORCA® Series 2 Field-Programmable Gate Arrays

Lattice Semiconductor 

Data Sheet

November 2006

ORCA Series 2 FPGAs

Bit Stream Error Checking

Table 10. Configuration Modes

There are three different types of bit stream error

checking performed in the ORCA Series 2 FPGAs:

M2 M1 M0 CCLK

Configuration

Mode

Data

ID frame, frame alignment, and parity checking.

0 0 0 Output Master

Serial

0 0 1 Input

Slave Parallel

Parallel

An optional ID data frame can be sent to a specified

address in the FPGA. This ID frame contains a unique

code for the part it was generated for which is com-

pared within the FPGA. Any differences are flagged as

S an ID error. This frame is automatically created by the

bit stream generation program in ispLEVER.

E Every data frame in the FPGA begins with a start bit

set to 0 and three or more stop bits set to 1. If any of

the three previous bits were a 0 when a start bit is

IC encountered, it is flagged as a frame alignment error.

D Parity checking is also done on the FPGA for each

frame, if it has been enabled by setting the prty_en bit

to 1 in the ID frame. This is set by enabling the parity

V E check option in the bit stream generation program of

ispLEVER. Two parity bits, opar and epar, are used to

check the parity of bits in alternating bit positions to

E U even parity in each data frame. If an odd number of

ones is found for either the even bits (starting with the

start bit) or the odd bits (starting with the program bit),

D IN then a parity error is flagged.

When any of the three possible errors occur, the FPGA

is forced into the INIT state, forcing INIT low. The FPGA

T T will remain in this state until either the RESET or PRGM

pins are asserted.

C N FPGA Configuration Modes

E There are eight methods for configuring the FPGA.

O Seven of the configuration modes are selected on the

L M0, M1, and M2 inputs. The eighth configuration mode

is accessed through the boundary-scan interface. A

E C fourth input, M3, is used to select the frequency of the

internal oscillator, which is the source for CCLK in

some configuration modes. The nominal frequencies of

S IS the internal oscillator are 1.25 MHz and 10 MHz. The

1.25 MHz frequency is selected when the M3 input is

unconnected or driven to a high state.

D There are three basic FPGA configuration modes:

0 1 0 Reserved

0 1 1 Input

Sync Peripheral Parallel

1 0 0 Output Master (up)

Parallel

1 0 1 Output Async Peripheral Parallel

1 1 0 Output Master (down) Parallel

1 1 1 Input

Slave

Serial

Master Parallel Mode

The master parallel configuration mode is generally

used to interface to industry-standard byte-wide mem-

ory, such as the 2764 and larger EPROMs. Figure 40

provides the connections for master parallel mode. The

FPGA outputs an 18-bit address on A[17:0] to memory

and reads one byte of configuration data on the rising

edge of RCLK. The parallel bytes are internally serial-

ized starting with the least significant bit, D0.

A[17:0]

A[17:0]

DOUT

CCLK

TO DAISY-

CHAINED

DEVICES

D[7:0]

EPROM

OE

CE

D[7:0]

DONE

ORCA

SERIES

FPGA

PROGRAM

VDD

VDD OR GND

PRGM

M2

M1

M0

HDC

LDC

RCLK

5-4483(F)

Figure 40. Master Parallel Configuration Schematic

There are two parallel master modes: master up and

master down. In master up, the starting memory

address is 00000 Hex and the FPGA increments the

address for each byte loaded. In master down, the

starting memory address is 3FFFF Hex and the FPGA

master, slave, and peripheral. The configuration data

decrements the address.

can be transmitted to the FPGA serially or in parallel

bytes. As a master, the FPGA provides the control sig- One master mode FPGA can interface to the memory

nals out to strobe data in. As a slave device, a clock is and provide configuration data on DOUT to additional

generated externally and provided into CCLK. In the

FPGAs in a daisy chain. The configuration data on

peripheral mode, the FPGA acts as a microprocessor

DOUT is provided synchronously with the falling edge

peripheral. Table 10 lists the functions of the configura- of CCLK. The frequency of the CCLK output is eight

tion mode pins.

times that of RCLK.

Lattice Semiconductor

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