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STM32F205RB 查看數據表(PDF) - STMicroelectronics

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STM32F205RB Datasheet PDF : 177 Pages
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Description
STM32F20xxx
Figure 6.
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
VDD
PDR=1.8 V
1.2 V
1.08 V
VCAP_1 /VCAP_2
time
PA0 tied to NRST
NRST
time
1. This figure is valid both whatever the internal reset mode (ON or OFF).
Figure 7.
Startup in regulator OFF: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
VDD
PDR=1.8 V
1.2 V
1.08 V
VCAP_1 /VCAP_2
time
PA0 asserted externally
NRST
time
2.2.17
Real-time clock (RTC), backup SRAM and backup registers
The backup domain of the STM32F20x devices includes:
The real-time clock (RTC)
4 Kbytes of backup SRAM
20 backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the second, minute, hour (in 12/24 hour), week day, date, month, year, in BCD (binary-coded
decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are
performed automatically. The RTC provides a programmable alarm and programmable
periodic interrupts with wakeup from Stop and Standby modes.
It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the internal low-power
RC oscillator or the high-speed external clock divided by 128. The internal low-speed RC
24/177
Doc ID 15818 Rev 9

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