STM32F407IGT7 查看數據表（PDF） - STMicroelectronics
零件编号
产品描述 (功能)
生产厂家
STM32F407IGT7 Datasheet PDF : 185 Pages
| |||
Electrical characteristics
STM32F405xx, STM32F407xx
Table 36. PLLI2S (audio PLL) characteristics (continued)
Symbol
Parameter
Conditions
Min Typ
Jitter(3)
Master I2S clock jitter
Cycle to cycle at
RMS
-
12.288 MHz on
48KHz period,
N=432, R=5
peak
to
-
peak
Average frequency of
12.288 MHz
N = 432, R = 5
-
on 1000 samples
90
±280
90
WS I2S clock jitter
Cycle to cycle at 48 KHz
on 1000 samples
-
400
IDD(PLLI2S)(4)
PLLI2S power consumption on
VDD
IDDA(PLLI2S)(4)
PLLI2S power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.30
0.55
-
1. Take care of using the appropriate division factor M to have the specified PLL input clock values.
2. Guaranteed by design, not tested in production.
3. Value given with main PLL running.
4. Based on characterization, not tested in production.
Max
-
-
-
-
0.40
0.75
0.40
0.85
Unit
ps
ps
ps
mA
mA
5.3.11
PLL spread spectrum clock generation (SSCG) characteristics
The spread spectrum clock generation (SSCG) feature allows to reduce electromagnetic
interferences (see Table 43: EMI characteristics). It is available only on the main PLL.
Table 37. SSCG parameters constraint
Symbol
Parameter
Min
fMod
md
MODEPER * INCSTEP
Modulation frequency
-
Peak modulation depth
0.25
-
1. Guaranteed by design, not tested in production.
Typ Max(1) Unit
-
10
KHz
-
2
%
-
215−1
-
Equation 1
The frequency modulation period (MODEPER) is given by the equation below:
MODEPER = round[fPLL_IN ⁄ (4 × fMod)]
fPLL_IN and fMod must be expressed in Hz.
As an example:
If fPLL_IN = 1 MHz, and fMOD = 1 kHz, the modulation depth (MODEPER) is given by
equation 1:
MODEPER = round[106 ⁄ (4 × 103)] = 250
102/185
DocID022152 Rev 4
Share Link: 