STM32F407RGH7 查看數據表（PDF） - STMicroelectronics
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STM32F407RGH7 Datasheet PDF : 185 Pages
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Electrical characteristics
STM32F405xx, STM32F407xx
5.3.19
Table 52. Characteristics of TIMx connected to the APB2 domain(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM) Timer resolution time
fEXT
ResTIM
tCOUNTER
Timer external clock
frequency on CH1 to
CH4
Timer resolution
16-bit counter clock
period when internal
clock is selected
AHB/APB2
prescaler distinct
from 1, fTIMxCLK =
168 MHz
AHB/APB2
prescaler = 1,
fTIMxCLK = 84 MHz
fTIMxCLK =
168 MHz
APB2 = 84 MHz
1
5.95
1
11.9
0
0
-
1
-
-
-
-
fTIMxCLK/2
84
16
65536
tMAX_COUNT Maximum possible count
-
32768
1. TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
tTIMxCLK
ns
tTIMxCLK
ns
MHz
MHz
bit
tTIMxCLK
tTIMxCLK
Communications interfaces
I2C interface characteristics
The STM32F405xx and STM32F407xx I2C interface meets the requirements of the
standard I2C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 53. Refer also to Section 5.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Symbol
tw(SCLL)
tw(SCLH)
tsu(SDA)
th(SDA)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
Table 53. I2C characteristics
Parameter
Standard mode I2C(1)
Min
Max
Fast mode I2C(1)(2)
Min
Max
SCL clock low time
SCL clock high time
SDA setup time
SDA data hold time
4.7
-
4.0
-
250
-
0(3)
-
1.3
-
0.6
-
100
-
0
900(4)
SDA and SCL rise time
-
1000 20 + 0.1Cb
300
SDA and SCL fall time
-
300
-
300
Unit
µs
ns
116/185
DocID022152 Rev 4
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