STM32F407ZEH7TR 查看數據表（PDF） - STMicroelectronics
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STM32F407ZEH7TR Datasheet PDF : 185 Pages
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Electrical characteristics
STM32F405xx, STM32F407xx
Table 67. ADC characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max Unit
fADC = 30 MHz
12-bit resolution
0.50
-
16.40
fADC = 30 MHz
10-bit resolution
0.43
-
16.34
tCONV(4)
Total conversion time (including
sampling time)
fADC = 30 MHz
8-bit resolution
0.37
-
16.27
fADC = 30 MHz
6-bit resolution
0.30
-
16.20
9 to 492 (tS for sampling +n-bit resolution for successive
approximation)
12-bit resolution
Single ADC
-
-
2
Sampling rate
fS(4) (fADC = 30 MHz, and
tS = 3 ADC cycles)
12-bit resolution
Interleave Dual ADC
-
mode
12-bit resolution
Interleave Triple ADC
-
mode
-
3.75
-
6
IVREF+(4)
ADC VREF DC current
consumption in conversion
mode
-
300
500
IVDDA(4)
ADC VDDA DC current
consumption in conversion
mode
-
1.6
1.8
µs
µs
µs
µs
1/fADC
Msps
Msps
Msps
µA
mA
1.
VanDDe/xVteDrDnAaml pinoiwmeurmsuvpaplulyesoufp1e.7rvVisoisr
obtained when the device
(refer to Section : Internal
operates in reduced
reset OFF).
temperature
range,
and
with
the
use
of
2. It is recommended to maintain the voltage difference between VREF+ and VDDA below 1.8 V.
3. VDDA -VREF+ < 1.2 V.
4. Based on characterization, not tested in production.
5. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA.
6. RADC maximum value is given for VDD=1.8 V, and minimum value for VDD=3.3 V.
7. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 67.
Equation 1: RAIN max formula
RAIN = f--A---D----C----×-----C-(--k--A---D-–--C---0--×--.--5-l-n---)-(---2---N----+----2----) – RADC
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. N = 12 (from 12-bit resolution) and k is the number of
sampling periods defined in the ADC_SMPR1 register.
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DocID022152 Rev 4
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