STM32F407RG 查看數據表（PDF） - STMicroelectronics

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STM32F407RG

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

Electrical characteristics

STM32F405xx, STM32F407xx

Table 74. DAC characteristics (continued)

Symbol

Parameter

Min Typ

Max

Unit

Comments

DAC_OUT Lower DAC_OUT voltage

min(2) with buffer OFF

DAC_OUT Higher DAC_OUT voltage

max(2) with buffer OFF

IVREF+(4)

DAC DC VREF current

consumption in quiescent

mode (Standby mode)

IDDA(4)

DAC DC VDDA current

consumption in quiescent

mode(3)

- 0.5

-

mV

It gives the maximum output

excursion of the DAC.

-

- VREF+ – 1LSB V

- 170

240

- 50

75

- 280

380

- 475

625

With no load, worst code (0x800)

at VREF+ = 3.6 V in terms of DC

consumption on the inputs

µA

With no load, worst code (0xF1C)

at VREF+ = 3.6 V in terms of DC

consumption on the inputs

µA

With no load, middle code (0x800)

on the inputs

With no load, worst code (0xF1C)

µA at VREF+ = 3.6 V in terms of DC

consumption on the inputs

DNL(4)

Differential non linearity

Difference between two

consecutive code-1LSB)

-

-

-

-

Integral non linearity

(difference between

-

-

INL(4)

measured value at Code i

and the value at Code i on a

line drawn between Code 0 -

-

and last Code 1023)

Offset error

-

-

(difference between

Offset(4) measured value at Code

-

-

(0x800) and the ideal value

= VREF+/2)

-

-

Gain

error(4)

Gain error

-

-

Settling time (full scale: for a

10-bit input code transition

tSETTLING(4)

between the lowest and the

highest input codes when

-

3

DAC_OUT reaches final

value ±4LSB

THD(4)

Total Harmonic Distortion

Buffer ON

-

-

±0.5

LSB

Given for the DAC in 10-bit

configuration.

±2

LSB

Given for the DAC in 12-bit

configuration.

±1

LSB

Given for the DAC in 10-bit

configuration.

±4

LSB

Given for the DAC in 12-bit

configuration.

±10

mV

Given for the DAC in 12-bit

configuration

±3

LSB

Given for the DAC in 10-bit at

VREF+ = 3.6 V

±12

LSB

Given for the DAC in 12-bit at

VREF+ = 3.6 V

±0.5

%

Given for the DAC in 12-bit

configuration

6

µs

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

-

dB

CLOAD ≤ 50 pF,

RLOAD ≥ 5 kΩ

136/185

DocID022152 Rev 4

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