STM32F405VEY7 查看數據表（PDF） - STMicroelectronics

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STM32F405VEY7

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

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Electrical characteristics

STM32F405xx, STM32F407xx

Asynchronous waveforms and timings

Figure 55 through Figure 58 represent asynchronous waveforms and Table 75 through

Table 78 provide the corresponding timings. The results shown in these tables are obtained

with the following FSMC configuration:

• AddressSetupTime = 1

• AddressHoldTime = 0x1

• DataSetupTime = 0x1

• BusTurnAroundDuration = 0x0

In all timing tables, the THCLK is the HCLK clock period.

Figure 55. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms

FSMC_NE

tv(NOE_NE)

tw(NE)

t w(NOE)

t h(NE_NOE)

FSMC_NOE

FSMC_NWE

FSMC_A[25:0]

FSMC_NBL[1:0]

tv(A_NE)

tv(BL_NE)

Address

t h(A_NOE)

t h(BL_NOE)

FSMC_D[15:0]

t v(NADV_NE)

tw(NADV)

tsu(Data_NOE)

tsu(Data_NE)

Data

t h(Data_NE)

th(Data_NOE)

FSMC_NADV(1)

1. Mode 2/B, C and D only. In Mode 1, FSMC_NADV is not used.

ai14991c

Table 75. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(NE)

tv(NOE_NE)

tw(NOE)

th(NE_NOE)

tv(A_NE)

th(A_NOE)

FSMC_NE low time

FSMC_NEx low to FSMC_NOE low

2THCLK–0.5 2 THCLK+1 ns

0.5

3

ns

FSMC_NOE low time

2THCLK–2 2THCLK+ 2 ns

FSMC_NOE high to FSMC_NE high hold time

0

-

ns

FSMC_NEx low to FSMC_A valid

-

4.5

ns

Address hold time after FSMC_NOE high

4

-

ns

138/185

DocID022152 Rev 4

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