STM32F405RET7TR 查看數據表（PDF） - STMicroelectronics

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STM32F405RET7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Electrical characteristics

Table 77. Asynchronous multiplexed PSRAM/NOR read timings(1)(2) (continued)

tv(NADV_NE)

tw(NADV)

th(AD_NADV)

FSMC_NEx low to FSMC_NADV low

FSMC_NADV low time

FSMC_AD(adress) valid hold time after

FSMC_NADV high)

1

2

ns

THCLK– 2

THCLK+1

ns

THCLK

-

ns

th(A_NOE) Address hold time after FSMC_NOE high

THCLK–1

-

ns

th(BL_NOE) FSMC_BL time after FSMC_NOE high

0

-

ns

tv(BL_NE) FSMC_NEx low to FSMC_BL valid

-

2

ns

tsu(Data_NE) Data to FSMC_NEx high setup time

THCLK+4

-

ns

tsu(Data_NOE) Data to FSMC_NOE high setup time

THCLK+4

-

ns

th(Data_NE) Data hold time after FSMC_NEx high

0

-

ns

th(Data_NOE) Data hold time after FSMC_NOE high

0

-

ns

1. CL = 30 pF.

2. Based on characterization, not tested in production.

Figure 58. Asynchronous multiplexed PSRAM/NOR write waveforms

tw(NE)

FSMC_NEx

FSMC_NOE

tv(NWE_NE)

tw(NWE)

t h(NE_NWE)

FSMC_NWE

FSMC_A[25:16]

FSMC_NBL[1:0]

FSMC_AD[15:0]

tv(A_NE)

tv(BL_NE)

t v(A_NE)

Address

t v(NADV_NE)

tw(NADV)

th(A_NWE)

Address

th(BL_NWE)

NBL

t v(Data_NADV)

Data

th(AD_NADV)

th(Data_NWE)

FSMC_NADV

ai14891B

Table 78. Asynchronous multiplexed PSRAM/NOR write timings(1)(2)

Symbol

Parameter

Min

Max

Unit

tw(NE)

tv(NWE_NE)

tw(NWE)

FSMC_NE low time

FSMC_NEx low to FSMC_NWE low

FSMC_NWE low tim e

4THCLK–0.5 4THCLK+3 ns

THCLK–0.5 THCLK -0.5 ns

2THCLK–0.5 2THCLK+3

ns

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