STM32F407REY7TR 查看數據表（PDF） - STMicroelectronics

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STM32F407REY7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Electrical characteristics

5.3.26

Table 86. Switching characteristics for NAND Flash write cycles(1)

Symbol

Parameter

Min

Max Unit

tw(NWE)

tv(NWE-D)

th(NWE-D)

td(D-NWE)

td(ALE-NWE)

th(NWE-ALE)

1. CL = 30 pF.

FSMC_NWE low width

FSMC_NWE low to FSMC_D[15-0] valid

FSMC_NWE high to FSMC_D[15-0] invalid

FSMC_D[15-0] valid before FSMC_NWE high

FSMC_ALE valid before FSMC_NWE low

FSMC_NWE high to FSMC_ALE invalid

4THCLK–1

-

4THCLK+ 3 ns

0

ns

3THCLK –2

-

ns

5THCLK–3

-

ns

-

3THCLK

ns

3THCLK–2

-

ns

Camera interface (DCMI) timing specifications

Unless otherwise specified, the parameters given in Table 87 for DCMI are derived from

tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage

summarized in Table 13, with the following configuration:

• PCK polarity: falling

• VSYNC and HSYNC polarity: high

• Data format: 14 bits

Figure 73. DCMI timing diagram

1/DCMI_PIXCLK

Pixel clock

HSYNC

VSYNC

DATA[0:13]

Symbol

tsu(HSYNC)

tsu(VSYNC)

tsu(DATA) th(DATA)

th(HSYNC)

th(HSYNC)

Table 87. DCMI characteristics(1)

Parameter

Min

MS32414V1

Max

Unit

Frequency ratio DCMI_PIXCLK/fHCLK

-

0.4

DCMI_PIXCLK

Dpixel

Pixel clock input

Pixel clock input duty cycle

-

54

MHz

30

70

%

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