STM32F405RET7TR 查看數據表（PDF） - STMicroelectronics

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STM32F405RET7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

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Revision history

STM32F405xx, STM32F407xx

Table 98. Document revision history (continued)

Date

Revision

Changes

31-May-2012

Removed fHSE_ext typical value in Table 29: High-speed external user

clock characteristics. Updated Table 31: HSE 4-26 MHz oscillator

characteristics and Table 32: LSE oscillator characteristics (fLSE =

32.768 kHz).

Added fPLL48_OUT maximum value in Table 35: Main PLL

characteristics.

Modified equation 1 and 2 in Section 5.3.11: PLL spread spectrum

clock generation (SSCG) characteristics.

Updated Table 38: Flash memory characteristics, Table 39: Flash

memory programming, and Table 40: Flash memory programming with

VPP.

Updated Section : Output driving current.

3

(continued)

Table 53: I2C characteristics: Note 4 updated and applied to th(SDA) in

Fast mode, and removed note 4 related to th(SDA) minimum value.

Updated Table 67: ADC characteristics. Updated note concerning ADC

accuracy vs. negative injection current below Table 68: ADC accuracy

at fADC = 30 MHz.

Added WLCSP90 thermal resistance in Table 96: Package thermal

characteristics.

Updated Table 90: WLCSP90 - 0.400 mm pitch wafer level chip size

package mechanical data.

Updated Figure 83: UFBGA176+25 - ultra thin fine pitch ball grid array

10 × 10 × 0.6 mm, package outline and Table 94: UFBGA176+25 -

ultra thin fine pitch ball grid array 10 × 10 × 0.6 mm mechanical data.

Added Figure 85: LQFP176 recommended footprint.

Removed 256 and 768 Kbyte Flash memory density from Table 97:

Ordering information scheme.

180/185

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