STM32F405OEY7TR 查看數據表（PDF） - STMicroelectronics

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STM32F405OEY7TR

ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM, USB OTG HS/FS, Ethernet, 17 TIMs, 3 ADCs, 15 comm. interfaces & camera

STMicroelectronics 

STM32F405xx, STM32F407xx

Revision history

Date

04-Jun-2013

Table 98. Document revision history (continued)

Revision

Changes

Modified Note 1 below Table 2: STM32F405xx and STM32F407xx:

features and peripheral counts.

Updated Figure 4 title.

Updated Note 3 below Figure 21: Power supply scheme.

Changed simplex mode into half-duplex mode in Section 2.2.25: Inter-

integrated sound (I2S).

Replaced DAC1_OUT and DAC2_OUT by DAC_OUT1 and

DAC_OUT2, respectively.

Updated pin 36 signal in Figure 15: STM32F40x LQFP176 pinout.

Changed pin number from F8 to D4 for PA13 pin in Table 7:

STM32F40x pin and ball definitions.

Replaced TIM2_CH1/TIM2_ETR by TIM2_CH1_ETR for PA0 and PA5

pins in Table 9: Alternate function mapping.

Changed system memory into System memory + OTP in Figure 18:

STM32F40x memory map.

Added Note 1 below Table 16: VCAP_1/VCAP_2 operating conditions.

Updated IDDA description in Table 74: DAC characteristics.

Removed PA9/PB13 connection to VBUS in Figure 86: USB controller

configured as peripheral-only and used in Full speed mode and

Figure 87: USB controller configured as host-only and used in full

speed mode.

Updated SPI throughput on front page and Section 2.2.24: Serial

peripheral interface (SPI)

4

Updated operating voltages in Table 2: STM32F405xx and

STM32F407xx: features and peripheral counts

Updated note in Section 2.2.14: Power supply schemes

Updated Section 2.2.15: Power supply supervisor

Updated “Regulator ON” paragraph in Section 2.2.16: Voltage

regulator

Removed note in Section 2.2.19: Low-power modes

Corrected wrong reference manual in Section 2.2.28: Ethernet MAC

interface with dedicated DMA and IEEE 1588 support

Updated Table 15: Limitations depending on the operating power

supply range

Updated Table 24: Typical and maximum current consumptions in

Standby mode

Updated Table 25: Typical and maximum current consumptions in

VBAT mode

Updated Table 36: PLLI2S (audio PLL) characteristics

Updated Table 43: EMI characteristics

Updated Table 48: Output voltage characteristics

Updated Table 50: NRST pin characteristics

Updated Table 55: SPI dynamic characteristics

Updated Table 56: I2S dynamic characteristics

Deleted Table 59

Updated Table 62: ULPI timing

Updated Figure 47: Ethernet SMI timing diagram

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