STM32F405RG 查看數據表（PDF） - STMicroelectronics
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STM32F405RG Datasheet PDF : 185 Pages
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STM32F405xx, STM32F407xx
Electrical characteristics
Table 15. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
state
(fFlashmax)
Maximum Flash
memory access
frequency
with wait
states(1) (2)
I/O operation
Clock output
Frequency on
I/O pins
Possible
Flash
memory
operations
V2.D1DV=(31).8 to
Conversion
time up to
1.2 Msps
20 MHz(4)
160 MHz with 7
wait states
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
8-bit erase
and program
operations
only
VDD = 2.1 to
2.4 V
Conversion
time up to
1.2 Msps
22 MHz
168 MHz with 7
wait states
– Degraded
speed
performance
– No I/O
compensation
up to 30 MHz
16-bit erase
and program
operations
VDD = 2.4 to
2.7 V
Conversion
time up to
2.4 Msps
24 MHz
168 MHz with 6
wait states
– Degraded
speed
performance
– I/O
compensation
works
up to 48 MHz
16-bit erase
and program
operations
V3.D6DV=(52).7 to
Conversion
time up to
2.4 Msps
30 MHz
168 MHz with 5
wait states
– Full-speed
operation
– I/O
compensation
works
– up to
60 MHz
when VDD =
3.0 to 3.6 V
– up to
48 MHz
when VDD =
2.7 to 3.0 V
32-bit erase
and program
operations
1. It applies only when code executed from Flash memory access, when code executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator and the 128-bit Flash memory, the number of wait states given here
does not impact the execution speed from Flash memory since the ART accelerator allows to achieve
a performance equivalent to 0 wait state program execution.
3.
VofDaDn/VeDxDteArnmalinpiomwuemr
value of 1.7 V is obtained
supply supervisor (refer to
when the
Section :
device operates in reduced
Internal reset OFF).
temperature
range,
and
with
the
use
4. Prefetch is not available. Refer to AN3430 application note for details on how to adjust performance and power.
5. The voltage range for OTG USB FS can drop down to 2.7 V. However it is degraded between 2.7 and 3 V.
5.3.2
VCAP_1/VCAP_2 external capacitor
Stabilization for the main regulator is achieved by connecting an external capacitor CEXT to
the VCAP_1/VCAP_2 pins. CEXT is specified in Table 16.
DocID022152 Rev 4
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