CS4391 查看數據表（PDF） - Cirrus Logic
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CS4391 Datasheet PDF : 38 Pages
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CS4391
Note:These clocking ratios are only available inControl Port Mode when the MCLK Divide bit is enabled.
Sample Rate
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
MCLK (MHz)
384x
512x
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
768x
24.5760
33.8688
36.8640
Table 8. Single Speed (4 to 50 kHz sample rates) Common Clock Frequencies
See Note
1024x
32.7680
45.1584
49.1520
Sample Rate
(kHz)
64
88.2
96
128x
8.1920
11.2896
12.2880
MCLK (MHz)
192x
256x
12.2880
16.3840
16.9344
22.5792
18.4320
24.5760
384x
24.5760
33.8688
36.8640
Table 9. Double Speed (50 to 100 kHz sample rates) Common Clock Frequencies
Sample Rate
(kHz)
176.4
192
64x
11.2896
12.2880
MCLK (MHz)
96x
128x
16.9344
22.5792
18.4320
24.5760
192x
33.8688
36.8640
Table 10. Quad Speed (100 to 200 kHz sample rates) Common Clock Frequencies
See Note
512x
32.7680
45.1584
49.1520
See Note
256x
45.1584
49.1520
M3
M1
M0
DESCRIPTION
(DIF1)
(DIF0)
0
0
0
Left Justified, up to 24-bit data
0
0
1
I2S, up to 24-bit data
0
1
0
Right Justified, 16-bit Data
0
1
1
Right Justified, 24-bit Data
FORMAT
0
1
2
3
FIGURE
7
8
9
10
Table 11. Single Speed (4 to 50 kHz) Digital Interface Format, Stand-Alone Mode Options
M3
M2
DESCRIPTION
(DEM)
0
0
No De-Emphasis
0
1
De-Emphasis Enabled
FIGURE
13
13
Table 12. Single Speed Only (4 to 50 kHz) De-Emphasis, Stand-Alone Mode Options
M3
M2
M1
M0
DESCRIPTION
1
0
0
0 Left Justified up to 24-bit data
1
0
0
1 I2S up to 24-bit data
1
0
1
0 Right Justified 16-bit data
1
0
1
1 Right Justified 24-bit data
FORMAT
0
1
2
3
FIGURE
7
8
9
10
Table 13. Double Speed (50 to 100 kHz) Digital Interface Format, Stand-Alone Mode Options
28
DS335PP4
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