ADE3700XT 查看數據表（PDF） - STMicroelectronics

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ADE3700XT

Analog LCD Display Engine for XGA and SXGA Resolutions

STMicroelectronics 

ADE3700

Register Name

PWM_CTRL1

PWM_PERIOD_L

PWM_PERIOD_H

PWM_DUTY_L

PWM_DUTY_H

PWM_OVERLAP_L

PWM_OVERLAP_H

PWM_STEP_DELAY

PWM_CYCLES_PER_FRAME_L

PWM_CYCLES_PER_FRAME_H

DFT Block

Table 33: PWM Registers (Sheet 2 of 2)

Addr

0x01A1

0x01A2

0x01A3

0x01A4

0x01A5

0x01A6

0x01A7

0x01A8

0x01A9

0x01AA

Mode Bits Default

Description

R/W

[7:4] 0x0

R/W

[3:0] 0x0

R/W

R/W

R/W

R/W

R/W

R/W

R/W

[7:0] 0x0

[7:0]

[7:0] 0x0

[7:0]

[7:0] 0x0

[7:0]

[7:0] 0x0

R/W

R/W

[7:0] 0x0

[7:0]

Lock 2nd order gain (power of 2)

0x0 = max

0x3 = typical

0xF = min.

Lock gain (power of 2)

0x0 = max

0x6 = typical

0xF = min.

Period-2 in free-running mode, in XCLKs

Duty cycle of PWM in XCLKs

Non-overlap of PWMs in XCLKs

In smooth change mode, the number of

cycles skipped before the period/duty

registers are incremented/decremented

The number of cycles per frame in frame

lock mode when not using the internally

generated cycles per frame from a previous

free-running mode

2.21 DFT Block

Register Name

DFT_TEST_MODE

DFT_MUX_OUT_MODE

DFT_FLOP_OUT_MODE

DFT_CLK_0UT_MODE

DFT_CLK_1_MODE

Table 34: DFT Registers (Sheet 1 of 3)

Addr

0x0F00

0x0F01

0x0F02

0x0F03

0x0F04

Mode Bits

[7:4]

R/W

[3]

R/W

[2]

R/W

[1]

R/W

[0]

[7:6]

R/W

[5:0]

[7:6]

R/W

[5:0]

R/W

[7:6]

R/W

[5:0]

R/W

[7:6]

Default

Description

Reserved

0x0

trigger video bus MFSR

0x0

enable output pin MFSR

0x0

clear output pin MFSR

0x0

output pin test override

Reserved

0x0

mux selector for output porta/b and syncs

Reserved

0x0

mux selector for synchronous digital debug

bus

0x0

divide-by selector for clocks to OCLK pin

fout = selected clock / (2 ^ value)

0x0

mux selector for clocks to OCLK pin

0x0

divide-by selector for clocks to CLKOUT

pin

fout = selected clock / (2 ^ value)

81/89

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