ADE3800SXT 查看數據表（PDF） - STMicroelectronics

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ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

ADE3800

Register Description by Block

Register Name

ANA_LVDSANA1

ANA_LVDSANA2

ANA_LVDSANA4

Table 41: LVDS/RSDS Registers (Sheet 2 of 5)

Address Bits Mode Rst

Description

0061

0062

0064

[7:6] R/W 00

[5:4] R/W

[3:2] R/W

[1:0] R/W

[7]

C0

[6]

[5:4] R/W

[3:2] R/W

[1:0] R/W

[6:4] R/W 01

[3]

[2]

[1]

[0]

Bit 3 Data Interface Delay Adjustment, see Bit 0

Bit 2 Data Interface Delay Adjustment, see Bit 0

Bit 1 Data Interface Delay Adjustment, see Bit 0

Bit 0 Data Interface Delay Adjustment

0*: 0ps (normal)

1: 90ps

2: 210ps

3: 460ps

PLL power control

0: on

1*: off

PLL Global Data Interface Delay

0: no delay

1*: delay (normal)

Bit 6 Data Interface Delay Adjustment, see Bit 0

Bit 5 Data Interface Delay Adjustment, see Bit 0

Bit 4 Data Interface Delay Adjustment, see Bit 0

LVDS Clock Skew

LSB = 135ps (typ)

LVDS Clock Skew Enable

0*: no delay (normal)

1: delay

LVDSclkout1 output polarity

0*: normal

1: invert

LVDSclkout0 output polarity

0*: normal

1: invert

LVDS & RSDS Master Power Control (Overrides

ANA_LVDSANA5[7], ANA_LVDSANA6[7], and

ANA_LVDSANA2[7])

115/138

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