ADE3800SXT 查看數據表（PDF） - STMicroelectronics

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ADE3800SXT

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

8-bit control covers amplitudes from 0.35V (00) to 1.05V (FF) in steps of 2.74mV.

OFFSET CONTROL

Red, Green, and Blue channels have independent control registers: ANA_ADC_RED_1,

ANA_ADC_GRN_1, and ANA_ADC_BLU_1, respectively.

6-bit control covers a range of ±92.8mV in steps of 2.9mV.

4.3.1

216MHz Frequency Synthesizer

The FS216 (controlled by the ANA_FS216_CTRL register) is the system PLL that drives the SCLK

and DCLK frequency synthesizers (refer to Section 4.2: Frequency Synthesizer (FSYN)) and the

LLK, by generating two different reference clock frequencies, 216=27x8 MHz (FSYN) and 54=27x2

MHz (LLK), based on XCLK.

For normal operation with a 27 MHz crystal, this register should be programmed to 0A.

The control register also allows for different crystal frequencies, power down, and optional use of an

external PLL.

4.3.2

Sync-on-Green (SOG)

It is necessary to tune the analog SOG circuit in order to secure a valid HSync that can be used by

the Line Lock PLL; the LLK may then be programmed to generate an in-clock. The ADC clamp

relies on in-clock and may only be enabled once this step is complete. Clamp pulse is used to set

the ADC black level reference voltage. In normal operation, the SOG signal is clamped by the ADC

clamp, and this clamp is not available during the initial tuning. For the initial tuning phase, instead of

the ADC clamp, the SOG clamp (pull down current) is used to clamp the input SOG signal. Once the

tuning has been accomplished, and there is a valid reference HSync and in-clock, the SOG clamp

may be disabled and the ADC clamp may be enabled.

There are therefore 2 states of sync-on-green operation: the initial state, which employs the SOG

clamp, and the normal (or locked) state, which employs the ADC clamp.

4.3.2.1 Initial SOG Clamp State

At power up, set:

● ANA_ADC_SOG_1[0] = 0 (power down bit; apply power to SOG),

● ANA_ADC_SOG_1[3] = 1 (enable SOG clamp pull down current),

● ANA_ADC_GRN_2[1] = 1 (ADC clamp off; must be the same as ANA_ADC_SOG_1[3]),

and adjust ANA_ADC_SOG_0[4:0] & ANA_ADC_SOG_1[7:4] until one of the three comparators

detects a SOG signal. Select a SOG signal to be the reference HSync to which the Line Lock PLL

will lock.

The normal value of the pull down current is 1.1uA and can be adjusted with

ANA_ADC_SOG_1[2:1]. Either ANA_ADC_SOG_1[0] = 1 or ANA_ADC_SOG_1[3] = 0 will turn off

the pull down current.

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