ADE3800SXL 查看數據表（PDF） - STMicroelectronics

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ADE3800SXL

Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

STMicroelectronics 

Register Description by Block

ADE3800

Synthesized signals are generated relative to the reference signal and selected edge.

Clean picture position wrap around is supported in both horizontal and vertical directions (+/- half a

line in horizontal and +/- half a frame in vertical).

Programmed position and size values must be less than the respective horizontal and vertical totals.

Figure 8: Block Diagram

input

signals

internal

signal

selector

H,V

reference

signals

hcount

vcount

output

signal

selector

output

signals

in_sel

ctrl1[3:0]

out_sel

Table 18: Sync Multiplexer Registers (Sheet 1 of 3)

Register Name

Addr Mode Bits Rst

Description

SMUX_CTRL_0

0200 R

[7]

00 toggle on vsync edge as programmed in bit 5

R/W [6]

0*: clamp on all lines

1: clamp not during coast

R/W [5]

v edge select

0*: falling

1: rising

R/W [4]

h edge select

0*: falling

1: rising

R/W [3:0]

input select

0*: llk_HSync, srt_vsync (normal)

1: HSYNC input signal, VSYNC input signal

2-E: reserved

F: HSync = TCON.SRTD6 output

VSync = TCON.SRTD7 output

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