EVAL-ADG902EB(RevA) 查看數據表（PDF） - Analog Devices
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EVAL-ADG902EB
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
EVAL-ADG902EB Datasheet PDF : 12 Pages
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ADG901/ADG902–SPECIFICATIONS1 (VDD = 1.65 V to 2.75 V, GND = 0 V, input power = 0 dBm,
all specifications TMIN to TMAX, unless otherwise noted.)
Parameter
Symbol Conditions
B Version
Min Typ2 Max
Unit
AC ELECTRICAL CHARACTERISTICS
Operating Frequency3
DC
2.5
–3 dB Frequency4
4.5
Input Power4
0 V dc Bias
7
+0.5 V dc Bias
16
Insertion Loss
Isolation—RF1 to RF2
(CP Package)
S21, S12
S21, S12
DC to 100 MHz; VDD = 2.5 V ± 10%
500 MHz; VDD = 2.5 V ± 10%
1000 MHz; VDD = 2.5 V ± 10%
100 MHz
60
500 MHz
43
0.4 0.7
0.5 0.8
0.8 1.25
61
45
1000 MHz
34
40
Isolation—RF1 to RF2
(RM Package)
S21, S12 100 MHz
500 MHz
51
60
37.5 47
Return Loss (On Channel)4
S11, S22
1000 MHz
DC to 100 MHz
500 MHz
31
37
20
28
23
29
Return Loss (Off Channel)4
S11, S22
1000 MHz
DC to 100 MHz
500 MHz
25
28
18
23
17
21
1000 MHz
15
19
On Switching Time4
Off Switching Time4
Rise Time4
Fall Time4
1 dB Compression4
Third Order Intermodulation Intercept
Video Feedthrough5
tON
tOFF
tRISE
tFALL
P–1 dB
IP3
50% CTRL to 90% RF
50% CTRL to 10% RF
10% to 90% RF
90% to 10% RF
1000 MHz
900 MHz/901 MHz, 4 dBm
3.6 6
5.8 9.5
3.1 5.5
6.0 8.5
17
30
36
2.5
GHz
GHz
dBm
dBm
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
ns
ns
ns
ns
dBm
dBm
mV p-p
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
Input Low Voltage
VINH
VINL
VINL
Input Leakage Current
II
CAPACITANCE4
RF1/RF2, RF Port On Capacitance
CTRL Input Capacitance
CRF ON
CCTRL
VDD = 2.25 V to 2.75 V
VDD = 1.65 V to 1.95 V
VDD = 2.25 V to 2.75 V
VDD = 1.65 V to 1.95 V
0 ≤ VIN ≤ 2.75 V
f = 1 MHz
f = 1 MHz
1.7
0.65 VCC
± 0.1
V
V
0.7
V
0.35 VCC V
±1
µA
1.2
pF
2.1
pF
POWER REQUIREMENTS
VDD
Quiescent Power Supply Current
IDD
Digital inputs = 0 V or VDD
1.65
2.75
V
0.1 1
µA
NOTES
1Temperature range B Version: –40°C to +85°C.
2Typical values are at VDD = 2.5 V and 25°C, unless otherwise stated.
3Point at which insertion loss degrades by 1 dB.
4Guaranteed by design, not subject to production test.
5The dc transience at the output of any port of the switch when the control voltage is switched from high to low or low to high in a 50 Ω test setup, measured with
1 ns rise time pulses and 500 MHz bandwidth.
Specifications subject to change without notice.
–2–
REV. A
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