ADSP-BF514BBCZ-3 查看數據表（PDF） - Analog Devices

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ADSP-BF514BBCZ-3

DSP Microcomputer

Analog Devices 

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

RESET

tRST_IN_PWR

CLKIN

VDD_SUPPLIES

Figure 8. Power-Up Reset Timing

Flash Reset Timing

Driving the RESET pin low resets the Flash device. Driving the

RESET pin high puts the device in normal operating mode. The

SO pin is in high impedance state while the device is in reset. A

successful reset will reset the status register to its power-up state.

See Table 25 for default power-up modes. A device reset during

an active Program or Erase operation aborts the operation and

data of the targeted address range may be corrupted or lost due

to the aborted erase or program operation. The device exits AAI

Programming Mode in progress and places the SO pin in high

impedance state.

Table 25. RESET Timing

Parameter

Timing Requirements

tRECR Reset Recovery from Read

tRECP Reset Recovery from Program

fRECE Reset Recovery from Erase

Min

Max

Unit

100

ns

10

μs

1

ms

SCK

RST

CE

tRECR

tRECP

tRECE

Figure 9. Flash Reset Timing

Rev. B | Page 28 of 68 | January 2011

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