ADSP-BF512BBCZ-4F4 查看數據表（PDF） - Analog Devices
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ADSP-BF512BBCZ-4F4 Datasheet PDF : 68 Pages
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ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
RSI Controller Timing
Table 31 and Figure 19 describe RSI controller timing. Table 32
and Figure 20 describe RSI controller (high speed) timing.
Table 31. RSI Controller Timing
Parameter
Min
Max
Timing Requirements
tISU Input Setup Time
5.6
tIH
Input Hold Time
2
Switching Characteristics
fPP1 Clock Frequency Data Transfer Mode
fOD Clock Frequency Identification Mode
tWL Clock Low Time
tWH Clock High Time
tTLH Clock Rise Time
tTHL Clock Fall Time
tODLY Output Delay Time During Data Transfer Mode
tODLY Output Delay Time During Identification Mode
0
25
1002
400
10
10
10
10
14
50
1 tPP = 1/fPP
2 Specification can be 0 kHz, which means to stop the clock. The given minimum frequency range is for cases where a continuous clock is required.
Unit
ns
ns
MHz
kHz
ns
ns
ns
ns
ns
ns
SD_CLK
INPUT
tPP
tTHL
tWL
tTLH
tWH
tISU
tIH
tODLY
OUTPUT
NOTES:
1 INPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
2 OUTPUT INCLUDES SD_Dx AND SD_CMD SIGNALS.
Figure 19. RSI Controller Timing
VOH (MIN)
VOL (MAX)
Rev. B | Page 35 of 68 | January 2011
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