ADSP-BF514BSWZ-4F4 查看數據表（PDF） - Analog Devices

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ADSP-BF514BSWZ-4F4

DSP Microcomputer

Analog Devices 

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F

JTAG Test And Emulation Port Timing

Table 49 and Figure 37 describe JTAG port operations.

Table 49. JTAG Port Timing

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS1

tHSYS1

System Inputs Setup Before TCK High

System Inputs Hold After TCK High

tTRSTW

TRST Pulse Width2 (measured in TCK cycles)

Switching Characteristics

20

ns

4

ns

4

ns

4

ns

5

ns

4

TCK

tDTDO

tDSYS3

TDO Delay from TCK Low

System Outputs Delay After TCK Low

10

ns

0

13

ns

1 System Inputs = DATA15–0, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH7–0, MDIO, TD1, TMS, RESET, NMI, BMODE2–0.

2 50 MHz Maximum

3 System Outputs = DATA15–0, ADDR19–1, ABE1–0, ARE, AWE, AMS1–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, TSCLK0, TFS0, RFS0, RSCLK0,

DT0PRI, DT0SEC, PF15–0, PG15–0, PH7–0, MDC, MDIO.

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tTCK

tSTAP

tDTDO

tSSYS

tDSYS

tHTAP

tHSYS

Figure 37. JTAG Port Timing

Rev. B | Page 49 of 68 | January 2011

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