AT87C54X2-3CSUL 查看數據表（PDF） - Atmel Corporation
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AT87C54X2-3CSUL Datasheet PDF : 62 Pages
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Figure 19-3. ICC Test Condition, Idle Mode
VCC
ICC
VCC
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
P0
EA
VCC
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 19-4. ICC Test Condition, Power-Down Mode
Reset = Vss after a high pulse
during at least 24 clock cycles
VCC
ICC
VCC
VCC
P0
RST EA
(NC)
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 19-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes
VCC-0.5V
0.45V
TCHCL
TCLCH
TCLCH = TCHCL = 5ns.
0.7VCC
0.2VCC-0.1
46 AT/TS8xC54/8X2
4431E–8051–04/06
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